preliminary ? 2000 fairchild semiconductor corporation ds500404 www.fairchildsemi.com august 2000 revised november 2000 FST32211 quad 12-bit to single 48-bit bus switch (preliminary) FST32211 quad 12-bit to single 48-bit bus switch (preliminary) general description the fairchild switch FST32211 provides up to 48-bits of high-speed cmos ttl-compatible bus switching. the low on resistance of the switch allows inputs to be connected to outputs without adding propagation delay or generating additional ground bounce noise. the device can be organized as four 12-bit, two 24-bit, or one 48-bit bus switch. when routed as a 40-bit bus switch, the device can be organized as four 10-bit, two 20-bit or one 40-bit bus switch. when oe 1 is low, the switch is on and port 1a is connected to port 1b. when oe 2 is low, the switch is on and port 2a is connected to port 2b. when oe 3 is low, the switch is on and port 3a is con- nected to port 3b. when oe 4 is low, the switch is on and port 4a is connected to port 4b. when oe 1 , oe 2 , oe 3 , or oe 4 are high, a high impedance state exists between the a and b ports. features 4 ? switch connection between two ports. minimal propagation delay through the switch. low l cc . zero bounce in flow-through mode. control inputs compatible with ttl level. also packaged in plastic fine pitch ball grid array (fbga) ordering code: bga package available in tape and reel only. logic diagram order number package number package description FST32211gx bga114a 114-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide
preliminary www.fairchildsemi.com 2 FST32211 connection diagram pin descriptions fbga pin assignments (40-bit routing) truth tables pin name description oe 1 , oe 2 , oe 3 , oe 4 bus switch enables 1a, 2a, 3a, 4a bus a 1b, 2b, 3b, 4b bus b 123 4 56 a 1a 2 1a 1 nc oe 2 1b 1 1b 2 b 1a 4 1a 3 gnd oe 1 1b 3 1b 4 c 1a 6 1a 5 gnd gnd 1b 5 1b 6 d 1a 8 1a 7 gnd gnd 1b 7 1b 8 e 1a 10 1a 9 v cc v cc 1b 9 1b 10 f 2a 2 2a 1 v cc v cc 2b 1 2b 2 g 2a 4 2a 3 v cc gnd 2b 3 2b 4 h 2a 6 2a 5 gnd gnd 2b 5 2b 6 j 2a 8 2a 7 2a 9 2b 9 2b 7 2b 8 k 2a 10 3a 10 gnd gnd 3b 10 2b 10 l 3a 9 3a 8 gnd gnd 3b 8 3b 9 m 3a 7 3a 6 gnd v cc 3b 6 3b 7 n 3a 5 3a 4 v cc v cc 3b 4 3b 5 p 3a 3 3a 2 v cc v cc 3b 2 3b 3 r 3a 1 4a 10 gnd gnd 4b 10 3b 1 t 4a 9 4a 8 gnd gnd 4b 8 4b 9 u 4a 7 4a 6 gnd 4b 1 4b 6 4b 7 v 4a 5 4a 4 4a 1 oe 4 4b 4 4b 5 w 4a 3 4a 2 oe 3 nc 4b 2 4b 3 inputs inputs/outputs oe 1 oe 2 1a, 1b 2a, 2b ll1a = 1b 2a = 2b lh1a = 1b z hlz2a = 2b hhz z inputs inputs/outputs oe 3 oe 4 3a, 3b 4a, 4b ll3a = 3b 4a = 4b lh3a = 3b z hlz4a = 4b hhz z
preliminary 3 www.fairchildsemi.com FST32211 connection diagram pin descriptions fbga pin assignments (48-bit routing) truth tables pin name description oe 1 , oe 2 , oe 3 , oe 4 bus switch enables 1a, 2a, 3a, 4a bus a 1b, 2b, 3b, 4b bus b 123 4 56 a 1a 2 1a 1 nc oe 2 1b 1 1b 2 b 1a 4 1a 3 1a 7 oe 1 1b 3 1b 4 c 1a 6 1a 5 gnd 1b 7 1b 5 1b 6 d 1a 10 1a 9 1a 8 1b 8 1b 9 1b 10 e 1a 12 1a 11 2a 1 2b 1 1b 11 1b 12 f 2a 4 2a 3 2a 2 2b 2 2b 3 2b 4 g 2a 6 2a 5 v cc nc 2b 5 2b 6 h 2a 8 2a 7 nc nc 2b 7 2b 8 j 2a 10 2a 9 2a 11 2b 11 2b 9 2b 10 k 2a 12 3a 12 nc nc 3b 12 2b 12 l 3a 11 3a 10 nc nc 3b 10 3b 11 m 3a 9 3a 8 gnd v cc 3b 8 3b 9 n 3a 7 3a 6 3a 2 3b 2 3b 6 3b 7 p 3a 5 3a 4 3a 1 3b 1 3b 4 3b 5 r 3a 3 4a 12 4a 8 4b 8 4b 12 3b 3 t 4a 11 4a 10 4a 7 4b 7 4b 10 4b 11 u 4a 9 4a 6 gnd 4b 1 4b 6 4b 9 v 4a 5 4a 4 4a 1 oe 4 4b 4 4b 5 w 4a 3 4a 2 oe 3 nc 4b 2 4b 3 inputs inputs/outputs oe 1 oe 2 1a, 1b 2a, 2b ll1a = 1b 2a = 2b lh1a = 1b z hlz2a = 2b hhz z inputs inputs/outputs oe 3 oe 4 3a, 3b 4a, 4b ll3a = 3b 4a = 4b lh3a = 3b z hlz4a = 4b hhz z
preliminary www.fairchildsemi.com 4 FST32211 absolute maximum ratings (note 1) recommended operating conditions (note 4) note 1: the ?absolute maximum ratings? are those values beyond which the safety of the device cannot be guaranteed. the device should not be operated at these limits. the parametric values defined in the electrical characteristics tables are not guaranteed at the absolute maximum rating. the ?recommended operating conditions? table will define the conditions for actual device operation. note 2: v s is the voltage observed/applied at either a or b ports across the switch. note 3: the input and output negative voltage ratings may be exceeded if the input and output diode current ratings are observed. note 4: unused control inputs must be held high or low. they may not float. dc electrical characteristics note 5: typical values are at v cc = 5.0v and t a = + 25 c note 6: measured by the voltage drop between a and b pins at the indicated current through the switch. on resistance is determined by t he lower of the voltages on the two (a or b) pins. supply voltage (v cc ) 0.5v to + 7.0v dc switch voltage (v s ) (note 2) ? 0.5v to + 7.0v dc input control pin voltage (v in )(note 3) ? 0.5v to + 7.0v dc input diode current (l ik ) v in < 0v ? 50ma dc output (i out ) 128ma dc v cc /gnd current (i cc /i gnd ) + / ? 100ma storage temperature range (t stg ) ? 65 c to + 150 c power supply operating (v cc) 4.0v to 5.5v input voltage (v in )0v to 5.5v output voltage (v out )0v to 5.5v input rise and fall time (t r , t f ) switch control input 0ns/v to 5ns/v switch i/o 0ns/v to dc free air operating temperature (t a )-40 c to + 85 c symbol parameter v cc (v) t a = ? 40 c to + 85 c units conditions min typ (note 5) max v ik clamp diode voltage 4.5 ? 1.2 v i in = ? 18ma v ih high level input voltage 4.0 ? 5.5 2.0 v v il low level input voltage 4.0 ? 5.5 0.8 v i i input leakage current 5.5 1.0 a0 v in 5.5v 010 av in = 5.5v i oz off-state leakage current 5.5 1.0 a0 a, b v cc r on switch on resistance 4.5 4 7 ? v in = 0v, i in = 64ma (note 6) 4.5 4 7 ? v in = 0v, i in = 30ma 4.5 8 12 ? v in = 2.4v, i in = 15ma 4.0 11 20 ? v in = 2.4v, i in = 15ma i cc quiescent supply current 5.5 3 aoe 1 = oe 2 = gnd v in = v cc or gnd, i out = 0 ? i cc increase in i cc per input 5.5 2.5 ma one input at 3.4v other inputs at v cc or gnd
preliminary 5 www.fairchildsemi.com FST32211 ac electrical characteristics note 7: this parameter is guaranteed by design but is not tested. the bus switch contributes no propagation delay other than the rc del ay of the typical on resistance of the switch and the 50pf load capacitance, when driven by an ideal voltage source (zero output impedance). capacitance (note 8) note 8: t a = + 25 c, f = 1 mhz, capacitance is characterized but not tested. ac loading and waveforms note: input driven by 50 ? source terminated in 50 ? note: c l includes load and stray capacitance note: input prr = 1.0 mhz, t w = 500 ns figure 1. ac test circuit figure 2. ac waveforms symbol parameter t a = ? 40 c to + 85 c, c l = 50pf, ru = rd = 500 ? units conditions figure no. v cc = 4.5 ? 5.5v v cc = 4.0v min max min max t phl ,t plh prop delay bus to bus (note 7) 0.25 0.25 ns v i = open figures 1, 2 t pzh , t pzl output enable time 1.5 6.0 6.5 ns v i = 7v for t pzl figures 1, 2 v i = open for t pzh t phz , t plz output disable time 1.5 7.0 7.2 ns v i = 7v for t plz figures 1, 2 v i = open for t phz symbol parameter typ max units conditions c in control pin input capacitance 3 pf v cc = 5.0v c i/o input/output capacitance 6 pf v cc , oe = 5.0v
preliminary www.fairchildsemi.com 6 FST32211 quad 12-bit to single 48-bit bus switch (preliminary) physical dimensions inches (millimeters) unless otherwise noted 114-ball fine-pitch ball grid array (fbga), jedec mo-205, 5.5mm wide package number bga114a technology description the fairchild switch family derives from and embodies fairchild ? s proven switch technology used for several years in its 74lvx3l384 (fst3384) bus switch product. fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and fairchild reserves the right at any time without notice to change said circuitry and specifications. life support policy fairchild ? s products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. a critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
|
